Recently, a phase change memory using chalcogenide materials as recording materials is studied actively. The phase change memory is a type of resistance change memory that stores information using that recording materials between electrodes have different resistance states.
The phase change memory stores information using that a resistance value of a phase change material such as Ge2Sb2Te5 is different in an amorphous state and a crystalline state. In the amorphous state, a resistance is high and in the crystalline state, the resistance is low. Therefore, information read from a memory cell is executed by applying a potential difference to both ends of an element, measuring a current flowing through the element, and determining a high resistance state/low resistance state of the element.
In the phase change memory, data is rewritten by changing an electrical resistance of a phase change film to a different state by a Joule heat generated by the current. A reset operation, that is, an operation for changing a state to the amorphous state of the high resistance is executed by flowing a large current for a short time, melting a phase change material, and decreasing the current rapidly for rapid cooling. Meanwhile, a set operation, that is, an operation for changing a state to the crystalline state of the low resistance is executed by flowing a current sufficient for maintaining the phase change material at a crystallization temperature for a long time. In the phase change memory, if miniaturization advances, a current necessary for changing a state of the phase change film decreases. For this reason, the phase change memory is miniaturized in principle. Therefore, a study is performed actively.
In PTL 1 described below, a configuration in which a plurality of through-holes penetrating entire layers are formed by collective processing in a lamination structure where a plurality of gate electrode materials and a plurality of insulating films are alternately laminated and a gate insulating film, a channel layer, and a phase change film are formed in the through-holes and are processed is disclosed as a method of highly integrating a phase change memory. Each memory cell includes a cell transistor and a phase change element that are connected in parallel and a plurality of memory cells are connected in series in a longitudinal direction, that is, a normal direction to a semiconductor substrate and form phase change memory chains. In a memory array configuration of PTL 1, each phase change memory chain is selected by a vertical selection transistor.
The phase change memory executes the reset/set/read operations by flowing a current to the memory cell. However, the magnitude of the flown current and an operation time are different in the three operations. A current necessary for the set operation is smaller than a current necessary for the reset operation. However, because the operation time of the set operation is long, an erasable cell number per unit time in the set operation is smaller than an erasable cell number per unit time in the reset operation. As a result, the throughput per consumption power decreases. To resolve such a problem, technology for flowing the current to adjacent memory cells at the same time, exchanging a Joule heat, and enabling the set operation for a large amount of memory cells unit per consumption power and per unit time is disclosed in PTL 2.
In the phase change memory, when the reset operation and the set operation are executed, it is necessary to flow a large current to the memory cells as compared with the read operation. Suppression of a voltage drop in an electrode wiring line for feeding the memory cells and securing of a drive current of a transistor or a selection transistor of a driver circuit may become a problem. With regard to an electrode for feeding, an electrode wiring line extending over the plurality of memory cells in a longitudinal direction, with a width almost equal to the magnitude of the memory cell, is used in PTL 1. Meanwhile, technology for providing the electrode wiring line for the feeding in a plate shape is disclosed in PTL 3.
In PTL 4, a configuration in which wiring lines (bit lines) for feeding the memory cells are connected to two power sources via separate transistors is disclosed. At the time of the set operation in which the operation is enabled with a small current as compared with the reset operation, only one power source is connected to a bit line by turning on the transistor and a sufficient current necessary for the set operation is flown to the memory cells. At the time of the reset operation, both the two transistors connecting the power sources and the bit lines are turned on and a large current necessary for the reset operation is flown to the memory cells.
In addition, technology for forming a selection transistor on a phase change memory chain is disclosed in PTL 5.